Optimization in mine planning could improve the economic benefit for mining companies. The main optimization contents in an underground mine includes stope layout, access layout and production scheduling. It is common to optimize each part sequentially, where optimal results from one phase are treated as the input for the next phase. The production schedule is based on the mining design. Access layout plays an important role in determining the connection relationships between stopes. This paper proposes a shortest-path search algorithm to design a network that automatically connects each stope. Access layout optimization is treated as a network flow problem. Stopes are viewed as nodes, and the roads between the stopes are regarded as edges. Moreover, the decline location influences the ore transport paths and haul distances. Tree diagrams of the ore transportation path are analyzed when each stope location is treated as an alternative decline location. The optimal decline location is chosen by an enumeration method. Then, Integer Programming (IP) is used to optimize the production scheduling process and maximize the Net Present Value (NPV). The extension sequence of access excavation and stope extraction is taken into account in the optimization model to balance access development and stope mining. These optimization models are validated in an application involving a hypothetical gold deposit, and the results demonstrate that the new approach can provide a more realistic solution compared with those of traditional approaches.

Operational amplifies (op amps) are an integral part of many analog and mixed-signal systems. Op amps with vastly different levels of complexity are used to realize functions ranging from DC bias generation to high-speed amplification or filtering. The design of op amps continues to pose a challenge as the supply voltage and transistor channel lengths scale down with each generation of CMOS technologies. The thesis deals with the analysis, design and layout optimization of CMOS op amps in deep Submicron (DSM) from a study case. Finally, layout optimizations of op amps will be given, in which propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design.