The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.

The article presents developed method and general principles of creating ladder diagrams, which are commonly used for systems with programmable logic controllers (PLC). Ladder diagrams are created for sequential control systems of technological processes, which are described by a connection pattern, time diagrams of the executive elements` operation. The executive elements are double-acting pneumatic or hydraulic actuators controlled by bistable electrovalves. A method of designing sequential systems enabling the creation of a ladder electro-pneumatic system is presented. The ladder diagram consists of two parts. One is responsible for controlling the valve coils, the other for the implementation of the memory block. The signals that control the transition to the next state are the signals described on the boundaries of the graph division. The synthesis of control systems and their verification was carried out using the computer aided program FluidSim by Festo.

Modern electrical-power systems are often exploited for transmitting highfrequency carrier signals for communications purposes. Series-connected air-core coils represent the fundamental component allowing such applications by providing a proper filtering in the frequency domain. They must be designed, however, to withstand also the line short-circuit current. When a high-magnitude current flows through a coil, strong mechanical stresses are produced within the conductor, leading to possible damage of the coil. In this paper, an approximate analytical model is derived for the relationship between the maximum mechanical stress and the electrical/geometrical parameters of the coil. Such a model provides the guidelines for a fast and safe coil design, whereas numerical simulations are only needed for the design refinement. The presented approach can be extended to other applications such as, for example, the mechanical stress resulting from the inrush currents in the coils of power transformers.

The presented paper concerns the issues of communication networks applied to monitoring and control of reactive power compensator for small hydroelectric plants installed in areas distant from urban agglomerations. Ethernet, CAN, Modbus and GPRS transmission protocols has been used. Industrial programmable controller as a data collector has been used also.

To overcome the detrimental influence of α impulse noise in power line communication and the trap of scarce prior information in traditional noise suppression schemes , a power iteration based fast independent component analysis (PowerICA) based noise suppression scheme is designed in this paper. Firstly, the pseudo-observation signal is constructed by weighted processing so that single-channel blind separation model is transformed into the multi-channel observed model. Then the proposed blind separation algorithm is used to separate noise and source signals. Finally, the effectiveness of the proposed algorithm is verified by experiment simulation. Experiment results show that the proposed algorithm has better separation effect, more stable separation and less implementation time than that of FastICA algorithm, which also improves the real-time performance of communication signal processing.

In this paper, the PLC-based (Programmable Logic Controller) industrial implementation in the form of the general-purpose function block for ADRC (Active Disturbance Rejection Controller) is presented. The details of practical aspects are discussed because their reliable implementation is not trivial for higher order ADRC. Additional important novelties discussed in the paper are the impact of the derivative backoff and the method that significantly simplifies tuning of higher order ADRC by avoiding the usual trial and error procedure. The results of the practical validation of the suggested concepts complete the paper and show the potential industrial applicability of ADRC.

The paper describes a prototype operator panel, which was designed to operate with the S7-200 family of Programmable Logic Controllers (PLC-s) from Siemens. Most of the functionality of the operator panel was implemented in a computer program, which runs on a PC-class computer. The program communicates with a PLC through its communication port configured in the Freeport mode. Two kinds of interface between the PC, and the PLC are supported: wired, and wireless. For wired connection a standard PC/PPI cable supplied by Siemens is used. For wireless connection two communication modules were designed, which operate in the free 433 MHz band. The operator panel program is intuitive, and easy to use. States of PLC inputs and outputs are presented using graphical objects. It is possible to modify states of the outputs, and monitor and edit any variable in the M and V memory in the PLC. The application supports also alarming. The program can be run on any computer with the MS Windows operating system installed. This makes the solution very cost-effective. Providing both wired and wireless communication radically increases flexibility of the proposed solution. The panel can be quickly mounted in areas, where pulling new cables is inconvenient, difficult or expensive.