Tytuł artykułu

Fast Determination of Similarity Between Two Vectors by Means of Analog CMOS Technique

Tytuł czasopisma

International Journal of Electronics and Telecommunications

Rocznik

2010

Wolumin

vol. 56

Numer

No 4

Autorzy

Wojtyna, Ryszard

Wydział PAN

Nauki Techniczne

Wydawca

Polish Academy of Sciences Committee of Electronics and Telecommunications

Data

2010

Identyfikator

DOI: 10.2478/v10177-010-0056-6 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Źródło

International Journal of Electronics and Telecommunications; 2010; vol. 56; No 4

Referencje

Ahalt S. (1990), Competitive learning algorithms for vector quantization, Neural Networks, 3, 131. ; Cauwenberghs G. (1999), Learning on silicon: Adaptive VLSI Neural Systems. ; Chen S.-L. (2008), A variable control system for wireless body sensor network, null, 2034. ; Chen Y. (1992), ANN with two-dendrite neurons and its weight initialization, null, 139. ; DeSieno D. (1988), Adding a conscience to competitive learning, null, 1, 117. ; Długosz R. (2006), New binary-tree-based Winner-Takes-All circuit for learning on silicon Kohonen's networks, null. ; Fakhraie S. (1997), VLSI-compatible implementations for artificial neural networks, doi.org/10.1007/978-1-4615-6311-2 ; Gatet L. (2009), Comparison between analog and digital neural network implementations for range-finding applications, IEEE Trans. Neural Netw, 20, 3. ; Holler M. (1989), An electrically trainable artificial neural network (ETANN) with 10240 ‘floating gate’ synapses, null, 191. ; Linares-Barranco B. (1993), A CMOS analog adaptive BAM with on-chip learning and weight refreshing, IEEE Trans. Neural Netw, 4, 3, 445. ; Macq D. (1993), Analog implementation of a Kohonen map with on-chip learning, IEEE Trans. Neural Netw, 4, 3, 456. ; Rajah A. (2004), ASIC design of a Kohonen Neural Network microchip, null, 148. ; Talaśka T. (2007), Adaptive weight change mechanism for Kohonens's Neural Network implemented in CMOS 0:18μm technology, null, 151. ; Wojtyna R. (2005), Simple CMOS transconductance-mode differential squarer, null, 171. ; Wojtyna R. (2006), Current-mode analog square rooter for hardware neuroprocessing, null. ; Wojtyna R. (2007), CMOS transconductance-mode analog circuit for fast determining Euclidean distance, Elektronika, 4, 65. ; Wojtyna R. (2009), Current-mode analog memory with extended storage time for hardware-implemented neural networks, Elektronika, 3, 34. ; Wojtyna R. (2004), Improved power-saving synapse for adaptive neuroprocessing on silicon, null, 27. ; Kohonen T. (2001), Self-Organizing Maps, doi.org/10.1007/978-3-642-56927-2