Title

UML Modelling in Rigorous Design Methodology for Discrete Controllers

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2012

Volume

vol. 58

Issue

No 1

Authors

Łabiak, Grzegorz ; Adamski, Marian ; Doligalski, Michał ; Tkacz, Jacek ; Bukowiec, Arkadiusz

Divisions of PAS

Nauki Techniczne

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2012

Identifier

DOI: 10.2478/v10177-012-0004-8 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Source

International Journal of Electronics and Telecommunications; 2012; vol. 58; No 1

References

Adamski M. (2005), Design of embedded control systems. ; Łabiak G. (2010), Statechart-based controllers synthesis in fpga structures with embedded array blocks, International Journal of Electronics and Telecommunications, 56, 1, 13, doi.org/10.2478/v10177-010-0002-7 ; Doligalski M. (2007), Partial reconfiguration-oriented design of logic controllers, null, 6937, 10. ; Booch G. (1999), The Unified Modeling Language. User Guide. ; Clarke E. (1999), Model Checking. ; Misurewicz P. (1976), Lecture Notes. ; Gniewek L. (2004), Hardware implementation of fuzzy Petri net as a controller, IEEE Transactions on Systems, Man, and Cybernetics - Part B: Cybernetics, 34, 3, 1315, doi.org/10.1109/TSMCB.2003.822956 ; Doligalski M. (2010), Exceptions and deep history state handling using dual specification, Electrical Review, 9, 123. ; čabiak G. (2008), Concurrent processes synchronisation in statecharts for FPGA implementation, null, 59. ; Biliński K. (1994), Petri-net-based algorithms for parallel-controller synthesis, IEE Proceedings - Computers and Digital Techniques, 141, 6, 405, doi.org/10.1049/ip-cdt:19941508 ; Karatkevich A. (2007), Dynamic Analysis of Petri Net-Based Discrete Systems, 356. ; Bukowiec A. (2009), Partitioning of Mealy finite state machines, null, 21. ; Wegrzyn A. (2005), Parallel algorithm for computation of deadlocks and traps in Petri nets, null, 143. ; Gallier J. (1985), Logic for Computer Science: Foundations of Automatic Theorem Proving. ; Tkacz J. (2007), State machine type colouring of Petri net by means of using a symbolic deduction method, Measurement Automation and Monitoring, 53, 5, 120. ; Adamski M. (1993), Petri nets in ASIC design, Applied Mathematics and Computer Science, 3, 1, 169. ; Zwoliński M. (2004), Digital System Design with VHDL. ; Puczyńska M. (2000), Programowa implementacja konwersji sieci petriego na jezyk VHDL, null, 285.