Details
Title
A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS TechnologyJournal title
International Journal of Electronics and TelecommunicationsYearbook
2021Volume
vol. 67Issue
No 3Authors
Affiliation
Khatak, Anil : Faculty of Biomedical Engineering, GJUS&T, Hisar, Haryana, India ; Kumar, Manoj : Faculty of USICT, Guru Gobind Singh Indraprastha University, New Delhi, India ; Dhull, Sanjeev : Faculty of ECE, GJUS&T, Hisar, Haryana, IndiaKeywords
Analog to Digital Converter (ADC) ; Successive Approximation Register (SAR) ; Common Mode Current Feedback Gain Boosting (CMFD-GB) ; Residue Amplifier (RA) ; Spurious freedynamic range (SFDR) ; Integral Non-Linearity (INL) ; Differential Non-Linearity (DNL)Divisions of PAS
Nauki TechniczneCoverage
347-354Publisher
Polish Academy of Sciences Committee of Electronics and TelecommunicationsBibliography
[1] Y. Zhou, B. Xu and Y. Chiu, “A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC,” IEEE Journal of Solid-State Circuits 54, 8, 2207-2218, (2019). https://doi.org/10.1109/JSSC.2019.2915583.[2] D. Oh, J. Kim, D. Jo, W. Kim, D. Chang and S. Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration,” IEEE Journal of Solid-State Circuits 54, 1, 288- 297,(2019). https://doi.org/10.1109/JSSC.2018.2870554.
[3] A. Wu, J. Wu, and J. Huang, “Energy-efficient switching scheme for ultra-low voltage SAR ADC.”, Analog Integr Circ Sig Process 90, 507–511, (2017). https://doi.org/10.1007/s10470-016-0892-0
[4] M. Guo, J. Mao, S. Sin, H. Wei and R. P. Martins, “A 1.6- GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration,”IEEE Journal of Solid-State Circuits 55, 3,693-705, (2020). https://doi.org/10.1109/JSSC.2019.2945298.
[5] M. Davidovic, G. Zach, H. Zimmermann, “An 11-bit successive approximation analog-to-digital converter based on a combined capacitor-resistor network.”, Elektrotech. Inftech. 127, 98–102, (2010). https://doi.org/10.1007/s00502-010-0704-7
[6] D. Chang, W. Kim, M. Seo, H. Hong, and S. Ryu, “Normalized- Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.”, IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, 322-332 (2017). https://doi.org/10.1109/TCSI.2016.2612692
[7] M. Shim et al.,“Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC”, IEEE Journal of Solid-State Circuits 52, 4, 1077-1090, (2017). https://doi.org/10.1109/JSSC.2016.2631299
[8] D. Zhang and A. Alvandpour, “A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs 63, 3, 244-248, (2016). https://doi.org/10.1109/TCSII.2015.2482618.
[9] S.A. Zahrai, M. Onabajo, “ Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power- Efficient Hybrid Data Converters.”, J. Low Power Electron. Appl. 8, 12, (2018). https://doi.org/10.3390/jlpea8020012
[10] S.Taheri, J. Lin, J. S. Yuan,“Security Interrogation and Defense for SAR Analog to Digital Converter.”, Electronics 6, 48, (2017). https://doi.org/10.3390/electronics6020048
[11] J. Kim, B. Sung, W. Kim and S. Ryu, “A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS”, IEEE Journal of Solid-State Circuits 48, 6, 1429-1441, (2013). https://doi.org/10.1109/JSSC.2013.2252516
[12] S. Danesh, J. Hurwitz, K. Findlater, D. Renshaw and R. Henderson, “A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design”, IEEE Journal of Solid-State Circuits 48, 3, 733-748, (2013). https://doi.org/10.1109/JSSC.2013.2237672
[13] L. Wang, M. LaCroix and A. C. Carusone, “A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.”, IEEE Transactions on Circuits and Systems II: Express Briefs 64, 12, 1367-1371, (2017). https://doi.org/10.1109/TCSII.2017.2726063
[14] F. M´arquez, et al., “A novel autozeroing technique for flash Analog-to-Digital converters.”, Integration 47, 1, 23-29, (2014). https://doi.org/10.1016/j.vlsi.2013.06.002
[15] Masumeh Damghanian, Seyed Javad Azhari, “A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications.”, Integration 57, 158-168, (2017). https://doi.org/10.1016/j.vlsi.2017.01.006
[16] Y. Wang, M. Yao, B. Guo, Z. Wu, W. Fan and J. J. Liou, “A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage,” IEEE Access 7, 93396- 93403,(2019). https://doi.org/10.1109/ACCESS.2019.2927514.
[17] A. Khatak, M. Kumar, S. Dhull, “An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits.”, J. Low Power Electron. Appl. 8, 33, (2018). https://doi.org/10.3390/jlpea8040033.
[18] B. Hershberg et al., “3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm,” 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA 68-70, (2019). https://doi.org/10.1109/ISSCC.2019.8662319.
[19] U. Chio et al., “Design and Experimental Verification of a Power Effective Flash-SAR Sub ranging ADC.”, IEEE Transactions on Circuits and Systems II: Express Briefs 57, 8, 607-611, (2010). https://doi.org/10.1109/TCSII.2010.2050937
[20] Young-Deuk Jeon et al., “A dual-channel pipelined ADC with sub-ADC based on flash-SAR architecture.”, Circuits and Systems II: Express Briefs 59, 741-745. (2012). https://doi.org/10.1109/TCSII.2012.2222837
[21] Y. Lin et al.,“ A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.”, IEEE Transactions on Circuits and Systems I: Regular Papers 60, 3, 570-581, (2013). https://doi.org/10.1109/TCSI.2012.2215756
[22] J.I. Lee, J. Song, “Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count.”, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013) 1-4, (2013). https://doi.org/10.1109/TENCON.2013.6718487
[23] A. Esmailiyan, F. Schembari and R. B. Staszewski, “A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump- Based Comparators in 28-nm CMOS,”IEEE Transactions on Circuits and Systems I: Regular Papers 67, 6, 1789-1802, (2020). https://doi.org/10.1109/TCSI.2020.2969804.
[24] J. Xu, et al., “Low-leakage analog switches for low-speed sample-and-hold circuits”, Microelectronics Journal 76, 22–27, (2018). https://doi.org/10.1016/j.mejo.2018.04.008
[25] M. Nazari, L. Sharifi,A. Aghajani, and O. Hashemipour, “A 12-bit high performance current-steering DAC using a new binary to thermometer decoder.”, 2016 24 Iranian Conference on Electrical Engineering (ICEE), Shiraz 2016 1919-1924, (2016). https://doi.org/10.1109/IranianCEE.2016.7585835
[26] H.S. Bindra et al., “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.”, IEEE Journal of Solid-State Circuits 53, 7, 1902-1912, (2018). https://doi.org/10.1109/JSSC.2018.2820147
[27] A. Taghizadeh, Z.D. Koozehkanani, J. Sobhi, “A new high-speed lowpower and low-offset dynamic comparator with a current-mode offset compensation technique.”, AEU - Int. J. Electron. Commun. 81, 163–170, (2018). https://doi.org/10.1016/j.aeue.2017.07.018.
[28] M. Saberi and R. Lotfi,“ Segmented Architecture for Successive Approximation Analog-to-Digital Converters.”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 3, 593-606, (2014). https://doi.org/10.1109/TVLSI.2013.2246592
[29] Y. Haga et al., “Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique.”, 2005 IEEE International Symposium on Circuits and Systems 1, 220-223, (2005). https://doi.org/10.1109/ISCAS.2005.1464564.
[30] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone- Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits 54, 3, 646-658, (2019). https://doi.org/10.1109/JSSC.2018.2889680.
[31] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC,” IEEE Journal of Solid-State Circuits 50, 12, 2901-2911, (2015). https://doi.org/10.1109/JSSC.2015.2463094
[32] B. Murmann, “The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.”, IEEE Communications Magazine 54, 4, 78-83, (2016). https://doi.org/10.1109/MCOM.2016.7452270
[33] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur196-199, (2010). https://doi.org/10.1109/APCCAS.2010.5774747.
[34] M. Hotta et al., “SAR ADC Architecture with Digital Error Correction.”. IEEJ Trans Elec Electron Eng 5, 651-659, (2010). https://doi.org/10.1002/tee.20588
[35] S. Lee, A.P. Chandrakasan and H. Lee, “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC with Background Timing Skew Calibration.”, IEEE Journal of Solid-State Circuits 49, 12, 2846-2856, (2014). https://doi.org/10.1109/JSSC.2014.2362851
[36] M. Damghanian and S.J. Azhari, “A novel three-section encoder in a low-power 2.3 GS/s flash ADC.”, Microelectronics J 82, 71–80, (2018). https://doi.org/10.1016/j.mejo.2018.10.009
[37] Yi. Shen and Z. Zhu, “Analysis and optimization of the twostage pipelined SAR ADCs.”, Microelectronics Journal 47, 1–5, (2016). https://doi.org/10.1016/j.mejo.2015.10.018.
[38] Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu,“A 10-bit 100-MS/s 5.23 mW SAR ADC in 0.18 μm CMOS.”,Microelectronics Journal 78, 63-72, (2018). https://doi.org/10.1016/j.mejo.2018.06.007
[39] X. Xin et al.,“A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip.”,Microelectronics Journal 83, 104–116, (2019). https://doi.org/10.1016/j.mejo.2018.11.017
[40] W. Guo, S. Liu, and Z. Zhu, “ An asynchronous 12-bit 50MS/s rail-torail Pipeline-SAR ADC in 0.18 μm CMOS.”, Microelectronics Journal 52, 23–30, (2016). https://doi.org/10.1016/j.mejo.2016.03.003
[41] B. Samadpoor Rikan et al.,“A 10-bit 1 MS / s segmented Dual-Sampling SAR ADC with reduced switching energy.”, Microelectronics Journal 70, 89–96, (2017). https://doi.org/10.1016/j.mejo.2017.11.005