Details
Title
Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal IntegrityJournal title
International Journal of Electronics and TelecommunicationsYearbook
2021Volume
vol. 67Issue
No 3Affiliation
Cheng, Kaixing : Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan University of Science and Engineering, Yibin, China ; Luo, Zhongqiang : Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan University of Science and Engineering, Yibin, China ; Xiong, Xingzhong : Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan University of Science and Engineering, Yibin, China ; Wei, Xiaohan : Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan University of Science and Engineering, Yibin, ChinaAuthors
Keywords
high-speed PCB ; signal integrity ; equal-length wiring ; HyperLynxDivisions of PAS
Nauki TechniczneCoverage
385-394Publisher
Polish Academy of Sciences Committee of Electronics and TelecommunicationsBibliography
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