This article presents the simulation of a BLDC motor and its closed control system in FPGA. The simulation is based on a mathematical model of the motor, including the electromagnetic torque, phase currents, back electromotive force, etc. In order to ensure calculation precision, the equations describing the motor were solved using a floating point representation of real numbers, and a small step of numerical calculations of 1 μs was assumed. The time step selection methodology has been discussed in detail. The motor model was executed with the use of Textual Programming Languages (with HDL codes).
The paper presents modification of the method dedicated to a complex area decomposition of a set of logic functions whereas the
altered method is dedicated to implement the considered logic circuits within FPGA structures. The authors attempted to reach solutions where the number of configurable logic blocks and the number of structural layer would be reasonably balanced on the basis of the minimization principle. The main advantage of the procedure when the decomposition is carried out directly on the BDD diagram is the opportunity of immediate checking whether the decomposed areas of the diagram do not exceed the resources of logic blocks incorporated into the integrated circuits that are used for implementation of the logic functions involved.
The cold start of the space GPS receiver, i.e. the start without any information about the receiver position, satellite constellation, and time, is complicated by a large Doppler shift of a navigation signal caused by the satellite movement on the Earth orbit. That increases about five times the search space of the navigation signals compared to the standard GPS receiver. The paper investigates a method of the acceleration of the GPS receiver cold start time designed for the pico- and femto-satellites. The proposed method is based on a combination of the parallel search in Doppler frequency and PRN codes and the serial search in code phase delay. It can shorten the cold start time of the GPS receiver operating on LEO orbit from about 300 to 60 seconds while keeping the simplicity of FPGA signal processor and low power consumption. The developed algorithm was successfully implemented and tested in the piNAV GPS receiver. The energy required for the obtaining of the position fix was reduced five times from 36 on to 7.7 Joules. This improvement enables applications of such receiver for the position determination in smaller satellites like Pocket Cube or femto-satellites with a lower energy budget than the Cube Satellite.
The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.
Mitigation of electromagnetic inference (EMI) is currently a challenge for scientists and designers in order to cope with electromagnetic compatibility (EMC) compliance in switching mode power supply (SMPS) and ensure the reliability of the whole system. Standard filtering techniques: passive and active ones present some insufficiency in terms of performance at high frequencies (HF) because analog components would no longer be controllable and this is mainly due to their parasitic elements. So developing EMI digital filters is very interesting, especially with the embedment of a machine control system on a field programmable gate array (FPGA) chip. In this paper, we present a design of an active digital EMI filter (ADF) to be integrated in a drive train system of an electric vehicle (EV). Hardware design as well as FPGA implementation issues have been presented to prove the efficiency of the developed digital filtering structure.
Department of Electrical Drive and Industrial Equipment University of Science and Technology (AGH) The article describes the method of determining mechanical losses and electromagnetic motor torque on the example of a flywheel energy storage system utilizing BLDC motor. The description of the test stand contains: the topology of power factor correction boost rectifier, an inverter supplying the BLDC motor, and the measuring system. The detailed experimental results are included in the paper.
The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.
This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.
The paper presents a solution of the control system for fatigue test stand MZGS-100 PL, comprising the integrated Real-Time controller based on FPGA (Field-Programmable Gate Array) technology with LabVIEW software. The described control system performs functions such as continuous regulation of speed induction motor, measuring strain of the lever machine and the test specimen, displacement of the polyharmonic vibrator, as well as the elimination of interferences, overload protection and emergency stop of the machine. The fatigue test stand also allows to set the pseudo-random history of energy parameter W(t).
In the past it was usual to exert a huge effort in the design, simulation, and the real time implementation of the complicated electronic and communication systems, like GNSS receivers. The complexity of the system algorithms combined with the complexity of the available tools created a system that is difficult to track down for debugging or for redesign. So, the simulation and educational tools was different from the prototyping tools. In this paper the parallel search acquisition phase of a GPS receiver was simulated and implemented on FPGA using the same platform and through a graphical programming language. So this paper introduces the fruit of integrating the prototyping tools with the simulation tools as a single platform through which the complicated electronic systems can be simulated and prototyped.
The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to make efficient use of the multigigabit optical fiber transmission and increasing the processing power of the FPGA/DSP/PC chips with optical I/O interfaces. The experiences with the development of the new generation of HOTN node based on the new technologies of data and functions concentration are extremely promising, because such systems are less expensive and require less labour.